1. Field of the Invention
The present invention relates to a power semiconductor device, and particularly to a semiconductor device with a power element and a circuit element formed within the same semiconductor substrate.
2. Description of the Background Art
Recently, a structure of a power semiconductor device has been developed in which a power element supplying electric power to a connected load and a circuit element controlling the power element are formed in the same semiconductor substrate. During a normal operation of the semiconductor device having the power element and the circuit element formed in the same semiconductor substrate, the potential of the semiconductor substrate does not become lower than the potential of a deep semiconductor layer of the p type (GND) which is a component of the circuit element. Therefore, during a normal operation, a parasitic element (parasitic NPN transistor) formed between the semiconductor substrate and an NMOS (N-channel Metal-Oxide-Semiconductor) which is a component of the circuit element does not operate and thus the semiconductor device does not malfunction.
However, in the case where negative current flows in the semiconductor device, the potential of the semiconductor substrate becomes lower than the potential of the deep p-type semiconductor layer which is a component of the circuit element. Accordingly, parasitic current flows from the p-type semiconductor layer to the semiconductor substrate, which causes the parasitic element to operate. As the parasitic element operates, the semiconductor device could malfunction.
Japanese Patent Laying-Open Nos. 2006-156959 and 06-350032 each disclose a configuration that does not allow a parasitic element formed in a semiconductor device to operate, and thus prevents the semiconductor device from malfunctioning.
In the semiconductor device disclosed in Japanese Patent Laying-Open No. 2006-156959, a first dummy region is formed between a power element's transistor and a circuit element and a second dummy region is formed between the transistor and an end of a semiconductor substrate, in order to prevent a parasitic element from operating. The first and second dummy regions are of a conductivity type different from that of the semiconductor substrate. The second dummy region is connected to a part of the semiconductor substrate that is located between the transistor and the first dummy region.
Further, in the semiconductor device disclosed in Japanese Patent Laying-Open No. 06-350032, an element isolation region and a GND line of an internal circuit are not directly connected by an interconnect layer which extends from a GND pad but connected through a resistive element, in order not to allow a parasitic element to operate.
In a semiconductor device having a power element and a circuit element formed in the same semiconductor substrate, a parasitic element is formed between the semiconductor substrate and an NMOS which is a component of the circuit element. When negative current flows in this semiconductor device, the potential of the semiconductor substrate becomes lower than the potential of a deep semiconductor layer of the p type which is a component of the circuit element, which causes the parasitic element to operate and thus causes malfunction of the semiconductor device.